Is Xilinx Shift Register Inferred By Code

Shift Registers

In general a shift register is characterized past the following control and data signals, which are fully recognized past XST:

clock
serial input
asynchronous fix/reset
synchronous set/reset
synchronous/asynchronous parallel load
clock enable
serial or parallel output. The shift register output style may be:
- serial: merely the contents of the last flip-bomb is accessed by the balance of the circuit
- parallel: the contents of ane or several of flip-flops other than the last one, is accessed
- shift modes: left, right, etc.

In that location are unlike ways to depict shift registers. For instance in VHDL y'all tin can utilize:

concatenation operator

                              shreg <= shreg (6 downto 0) & SI;

"for loop" construct

for i in 0 to 6 loop   shreg(i+1) <= shreg(i);  end loop;  shreg(0) <= SI;

predefined shift operators for case, sll, srl.

Consult the VHDL/Verilog language reference manuals for more information.

FPGAs:

Before writing Shift Register behavior it is important to recall that Virtex, Virtex-E, Virtex-Two, and Virtex-II Pro have specific hardware resource to implement Shift Registers: SRL16 for Virtex and Virtex-East, and SRLC16 for Virtex-2 and Virtex-Two Pro. Both are available with or without a clock enable. The following figure shows the pin layout of SRL16E.

The following figure shows the pin layout of SRLC16.

Notation Synchronous and asynchronous control signals are not bachelor in the SLRC16x primitives.

However, SRL16 and SRLC16 support only LEFT shift performance for a limited number of IO signals:

Clock
Clock enable
Serial data in
Serial data out

It means, that if your shift register does accept, for instance, a synchronous parallel load, no SRL16 volition be implemented. XST will non attempt to infer SR4x, SR8x or SR16x macros. It volition apply specific internal processing which allows information technology to bring the best final results.

The XST log file reports recognized shift registers when it can be implemented using SRL16.

Log File

The XST log file reports the type and size of recognized shift registers during the macro recognition step:


... Synthesizing Unit of measurement <shift>. Related source file is shift_registers_1.vhd. Constitute 8-bit shift register for signal <tmp<7>>. Summary: inferred 1 Shift register(s). Unit <shift> synthesized. ============================== HDL Synthesis Report Macro Statistics # Shift Registers : 1 8-bit shift register : 1 ============================== ...

Related Constraints

A related constraint is shreg_extract.

viii-bit Shift-Left Annals with Positive-Border Clock, Serial In, and Serial Out

Annotation For this example, XST will infer SRL16.

The following tabular array shows pin definitions for an 8-bit shift-left register with a positive-edge clock, serial in, and serial out.


IO Pins	Description
C	Positive-Border Clock
SI	Serial In
So	Series Output

VHDL Lawmaking

Following is the VHDL code for an viii-chip shift-left register with a positive-edge clock, serial in, and serial out.

library ieee;  use ieee.std_logic_1164.all;    entity shift is    port(C, SI : in  std_logic;          So : out std_logic);  end shift;  compages archi of shift is    signal tmp: std_logic_vector(7 downto 0);    begin      procedure (C)        begin          if (C'event and C='i') and so            for i in 0 to 6 loop              tmp(i+i) <= tmp(i);            cease loop;            tmp(0) <= SI;          end if;      end procedure;      So <= tmp(7);  cease archi;

Verilog Code

Following is the Verilog code for an viii-bit shift-left register with a positive-edge clock, serial in, and series out.

module shift (C, SI, And so);  input C,SI;  output SO;  reg [seven:0] tmp;      always @(posedge C)      begin        tmp = tmp << 1;        tmp[0] = SI;      terminate      assign Then  = tmp[7];  endmodule

viii-bit Shift-Left Annals with Negative-Edge Clock, Clock Enable, Serial In, and Serial Out

Note For this example, XST volition infer SRL16E_1.

The following tabular array shows pin definitions for an 8-chip shift-left annals with a negative-edge clock, clock enable, serial in, and serial out.


IO Pins	Clarification
C	Negative-Edge Clock
SI	Serial In
CE	Clock Enable (active Loftier)
SO	Serial Output

VHDL Code

Following is the VHDL code for an viii-bit shift-left register with a negative-edge clock, clock enable, serial in, and serial out.

library ieee;  use ieee.std_logic_1164.all;

entity shift is

  port(C, SI, CE : in  std_logic;          SO : out std_logic);  finish shift;  architecture archi of shift is    signal tmp: std_logic_vector(seven downto 0);    begin      process (C)        begin           if (C'outcome and C='0') then            if (CE='ane') then              for i in 0 to six loop                tmp(i+1) <= tmp(i);              end loop;                tmp(0) <= SI;            stop if;          end if;      finish process;      So <= tmp(seven);  finish archi;

Verilog Code

Following is the Verilog code for an 8-bit shift-left register with a negative-edge clock, clock enable, serial in, and serial out.

module shift (C, CE, SI, SO);  input C,SI, CE;  output Then;  reg [7:0] tmp;      always @(negedge C)      brainstorm        if (CE)          begin            tmp = tmp << 1;            tmp[0] = SI;          finish      end      assign SO  = tmp[7];  endmodule

8-bit Shift-Left Annals with Positive-Edge Clock, Asynchronous Clear, Serial In, and Serial Out

Note Because this example includes an asynchronous clear, XST will not infer SRL16.

The post-obit table shows pin definitions for an 8-scrap shift-left register with a positive-edge clock, asynchronous clear, serial in, and series out.


IO Pins	Description
C	Positive-Edge Clock
SI	Serial In
CLR	Asynchronous Clear (agile High)
And then	Serial Output

VHDL Code

Post-obit is the VHDL code for an 8-bit shift-left register with a positive-border clock, asynchronous clear, serial in, and series out.

library ieee;  use ieee.std_logic_1164.all;    entity shift is    port(C, SI, CLR : in std_logic;          And then : out std_logic);  end shift;  architecture archi of shift is    point tmp: std_logic_vector(vii downto 0);    begin      process (C, CLR)        brainstorm          if (CLR='ane') then            tmp <= (others => '0');          elsif (C'event and C='i') and so            tmp <= tmp(6 downto 0) & SI;          terminate if;      end process;      Then <= tmp(7);  end archi;

Verilog Code

Following is the Verilog code for an 8-bit shift-left annals with a positive-edge clock, asynchronous articulate, serial in, and serial out.

module shift (C, CLR, SI, SO);  input  C,SI,CLR;  output SO;  reg [7:0] tmp;      always @(posedge C or posedge CLR)    begin      if (CLR)        tmp = 8'b00000000;      else        begin          tmp = {tmp[six:0], SI};        finish     finish    assign Then  = tmp[7];  endmodule

8-fleck Shift-Left Register with Positive-Edge Clock, Synchronous Gear up, Serial In, and Series Out

Note Because this instance includes an asynchronous clear XST volition not infer SRL16.

The following table shows pin definitions for an viii-bit shift-left register with a positive-edge clock, synchronous gear up, serial in, and serial out.


IO Pins	Clarification
C	Positive-Edge Clock
SI	Series In
S	synchronous Set (active High)
So	Serial Output

VHDL Lawmaking

Following is the VHDL code for an 8-bit shift-left register with a positive-border clock, synchronous fix, serial in, and serial out.

library ieee;  use ieee.std_logic_1164.all;    entity shift is    port(C, SI, S : in  std_logic;          Then : out std_logic);  cease shift;  compages archi of shift is    bespeak tmp: std_logic_vector(7 downto 0);    brainstorm      process (C, S)        begin          if (C'event and C='i') so            if (S='1') and so              tmp <= (others => '1');            else               tmp <= tmp(six downto 0) & SI;            stop if;          finish if;      terminate process;      And then <= tmp(seven);  end archi;

Verilog Lawmaking

Post-obit is the Verilog code for an eight-bit shift-left annals with a positive-edge clock, synchronous prepare, serial in, and serial out.

module shift (C, Southward, SI, And so);

input  C,SI,S;  output And so;  reg [7:0] tmp;      e'er @(posedge C)    begin      if (S)        tmp = viii'b11111111;      else        begin          tmp = {tmp[6:0], SI};        end    finish    assign SO  = tmp[7];  endmodule

8-chip Shift-Left Register with Positive-Edge Clock, Serial In, and Parallel Out

Note For this case XST will infer SRL16.

The following table shows pin definitions for an 8-bit shift-left register with a positive-edge clock, serial in, and serial out.


IO Pins	Description
C	Positive-Border Clock
SI	Serial In
PO[seven:0]	Parallel Output

VHDL Lawmaking

Post-obit is the VHDL lawmaking for an 8-bit shift-left register with a positive-edge clock, serial in, and series out.

library ieee;  utilize ieee.std_logic_1164.all;    entity shift is     port(C, SI : in  std_logic;          PO : out std_logic_vector(7 downto 0));  end shift;  architecture archi of shift is    signal tmp: std_logic_vector(seven downto 0);    begin      process (C)        begin           if (C'event and C='i') and then             tmp <= tmp(vi downto 0)& SI;          end if;      end procedure;      PO <= tmp;  end archi;

Verilog Code

Following is the Verilog code for an viii-bit shift-left register with a positive-edge clock, serial in, and serial out.

module shift (C, SI, PO);  input  C,SI;  output [seven:0] PO;  reg [vii:0] tmp;      ever @(posedge C)    begin      tmp = {tmp[6:0], SI};    finish    assign PO = tmp;  endmodule

8-chip Shift-Left Annals with Positive-Edge Clock, Asynchronous Parallel Load, Serial In, and Serial Out

Annotation For this instance XST will infer SRL16.

The following tabular array shows pin definitions for an 8-bit shift-left register with a positive-border clock, asynchronous parallel load, serial in, and serial out.


IO Pins	Clarification
C	Positive-Edge Clock
SI	Series In
ALOAD	Asynchronous Parallel Load (active High)
D[seven:0]	Data Input
SO	Serial Output

VHDL Code

Following is VHDL code for an 8-bit shift-left annals with a positive-edge clock, asynchronous parallel load, serial in, and serial out.

library ieee;  use ieee.std_logic_1164.all;  entity shift is    port(C, SI, ALOAD : in std_logic;          D   : in std_logic_vector(7 downto 0);          SO  : out std_logic);  finish shift;  compages archi of shift is    signal tmp: std_logic_vector(7 downto 0);    begin       process (C, ALOAD, D)        brainstorm          if (ALOAD='1') then            tmp <= D;          elsif (C'event and C='ane') then            tmp <= tmp(half-dozen downto 0) & SI;          finish if;      end process;      SO <= tmp(seven);  end archi;

Verilog Code

Following is the Verilog code for an 8-flake shift-left annals with a positive-edge clock, asynchronous parallel load, serial in, and series out.

module shift (C, ALOAD, SI, D, Then);  input  C,SI,ALOAD;  input [vii:0] D;  output So;  reg [7:0] tmp;      e'er @(posedge C or posedge ALOAD)    brainstorm      if (ALOAD)        tmp = D;      else        begin          tmp = {tmp[half dozen:0], SI};        finish    end    assign SO  = tmp[7];  endmodule

viii-bit Shift-Left Register with Positive-Edge Clock, Synchronous Parallel Load, Serial In, and Serial Out

Note For this example XST will non infer SRL16.

The post-obit table shows pin definitions for an 8-chip shift-left register with a positive-edge clock, synchronous parallel load, series in, and serial out.


IO Pins	Description
C	Positive-Border Clock
SI	Series In
SLOAD	Synchronous Parallel Load (active Loftier)
D[7:0]	Data Input
SO	Serial Output

VHDL Lawmaking

Post-obit is the VHDL code for an 8-fleck shift-left annals with a positive-edge clock, synchronous parallel load, serial in, and serial out.

library ieee;  use ieee.std_logic_1164.all;    entity shift is    port(C, SI, SLOAD : in std_logic;          D  : in std_logic_vector(7 downto 0);          And so : out std_logic);  terminate shift;  architecture archi of shift is    point tmp: std_logic_vector(7 downto 0);    brainstorm      procedure (C)        begin          if (C'event and C='ane') then            if (SLOAD='1') so              tmp <= D;            else              tmp <= tmp(6 downto 0) & SI;            end if;          finish if;      end process;      SO <= tmp(seven);  end archi;

Verilog Lawmaking

Following is the Verilog lawmaking for an 8-bit shift-left register with a positive-edge clock, synchronous parallel load, serial in, and series out.

module shift (C, SLOAD, SI, D, And then);  input  C,SI,SLOAD;  input [7:0] D;  output SO;  reg [seven:0] tmp;      always @(posedge C)    begin      if (SLOAD)        tmp = D;      else        begin          tmp = {tmp[6:0], SI};        end    end    assign SO  = tmp[7];  endmodule

8-bit Shift-Left/Shift-Right Register with Positive-Border Clock, Serial In, and Parallel Out

Note For this instance XST volition not infer SRL16.

The following table shows pivot definitions for an 8-flake shift-left/shift-right register with a positive-edge clock, series in, and serial out.


IO Pins	Clarification
C	Positive-Edge Clock
SI	Serial In
LEFT_RIGHT	Left/correct shift way selector
PO[7:0]	Parallel Output

VHDL Code

Post-obit is the VHDL code for an eight-bit shift-left/shift-right annals with a positive-edge clock, series in, and serial out.

library ieee;  employ ieee.std_logic_1164.all;    entity shift is  port(C, SI, LEFT_RIGHT : in std_logic;        PO : out std_logic_vector(7 downto 0));  end shift;  architecture archi of shift is    signal tmp: std_logic_vector(vii downto 0);    begin      process (C)        begin          if (C'effect and C='1') so            if (LEFT_RIGHT='0') then              tmp <= tmp(half dozen downto 0) & SI;            else              tmp <= SI & tmp(seven downto 1);            terminate if;          end if;      finish procedure;      PO <= tmp;  end archi;

Verilog Code

Post-obit is the Verilog code for an 8-flake shift-left/shift-right annals with a positive-edge clock, serial in, and serial out.

module shift (C, SI, LEFT_RIGHT, PO);

input  C,SI,LEFT_RIGHT;  output PO;  reg [seven:0] tmp;      always @(posedge C)    brainstorm      if (LEFT_RIGHT==i'b0)        begin          tmp = {tmp[6:0], SI};        end      else        begin          tmp = {SI, tmp[6:0]};        end    end    assign PO  = tmp;  endmodule